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systems

Available system targets.

These are the systems you can execute your solutions on.

01 available systems
Raptor Cove P-core raptor_cove_p
uarch Raptor Cove
core class P-core
Cores
1
Cache
48 KiB L1D 12-way, 32 KiB L1I 8-way, 1.25 MiB private L2 10-way, 24 MiB shared L3 12-way, 64 B lines.
DRAM
2 x 32 GiB DDR4-3200 UDIMM, 2 channels, 2 ranks/DIMM, x8 SDRAM, 4 bank groups x 4 banks/device.
Front end
6 decoders, 8-wide uop cache, improved branch prediction for larger code footprints.
OoO engine
6-wide allocate, 512-entry reorder buffer, 12 execution ports.
ISA highlights
AVX2, AVX-VNNI, FMA, BMI1/2, POPCNT/LZCNT, AES/SHA-NI, GFNI, VAES, VPCLMULQDQ.
Wikimedia Commons block diagram of Intel Golden Cove P-core architecture
Golden Cove-family P-core diagram shown for the Raptor Cove worker. Golden Cove.png by Saneandsad, licensed CC BY-SA 4.0 via Wikimedia Commons.
Gracemont E-core gracemont_e
uarch Gracemont
core class E-core
Cores
1
Cache
32 KiB L1D 8-way, 64 KiB L1I 8-way, 2 MiB L2 16-way per 4-core cluster, 24 MiB shared L3 12-way, 64 B lines.
DRAM
2 x 32 GiB DDR4-3200 UDIMM, 2 channels, 2 ranks/DIMM, x8 SDRAM, 4 bank groups x 4 banks/device.
Front end
Clustered decoder, up to 6 instructions/cycle, 64 KiB instruction cache, on-demand instruction length decoder.
OoO engine
5-wide allocate, 8-wide retire, 256-entry out-of-order window, 17 execution ports.
ISA highlights
AVX2, AVX-VNNI, FMA, BMI1/2, POPCNT/LZCNT, AES/SHA-NI, GFNI, VAES, VPCLMULQDQ.
Wikimedia Commons block diagram of Intel Gracemont E-core architecture
Gracemont E-core diagram shown for the E-core worker. GracemontRevised.png by Saneandsad, licensed CC BY-SA 4.0 via Wikimedia Commons.
02 raptor lake die
Labelled Intel Core i9-13900K Raptor Lake die shot
Raptor Lake family i9-13900K die shot shown for orientation; the current host is an i5-13500. Image by JmsDoug and Fritzchens Fritz, licensed CC0 via Wikimedia Commons.