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systems

Registered system targets.

Enabled systems receive jobs for every submission. Staging systems are registered but do not schedule work yet.

01 registered systems
Raptor Cove P-core active raptor_cove_p
uarch Raptor Cove
core class P-core
Cores
1
Cache
48 KiB L1D 12-way, 32 KiB L1I 8-way, 1.25 MiB private L2 10-way, 24 MiB shared L3 12-way, 64 B lines.
DRAM
2 x 32 GiB DDR4-3200 UDIMM, 2 channels, 2 ranks/DIMM, x8 SDRAM, 4 bank groups x 4 banks/device.
Front end
6 decoders, 8-wide uop cache, improved branch prediction for larger code footprints.
OoO engine
6-wide allocate, 512-entry reorder buffer, 12 execution ports.
ISA highlights
AVX2, AVX-VNNI, FMA, BMI1/2, POPCNT/LZCNT, AES/SHA-NI, GFNI, VAES, VPCLMULQDQ.
Measurement noise
Samples- Minimum delta- Median baseline- Mean delta- Maximum delta- Sigma-
Wikimedia Commons block diagram of Intel Golden Cove P-core architecture
Golden Cove-family P-core diagram shown for the Raptor Cove worker. Golden Cove.png by Saneandsad, licensed CC BY-SA 4.0 via Wikimedia Commons.
Timing delta from median
period
Gracemont E-core active gracemont_e
uarch Gracemont
core class E-core
Cores
1
Cache
32 KiB L1D 8-way, 64 KiB L1I 8-way, 2 MiB L2 16-way per 4-core cluster, 24 MiB shared L3 12-way, 64 B lines.
DRAM
2 x 32 GiB DDR4-3200 UDIMM, 2 channels, 2 ranks/DIMM, x8 SDRAM, 4 bank groups x 4 banks/device.
Front end
Clustered decoder, up to 6 instructions/cycle, 64 KiB instruction cache, on-demand instruction length decoder.
OoO engine
5-wide allocate, 8-wide retire, 256-entry out-of-order window, 17 execution ports.
ISA highlights
AVX2, AVX-VNNI, FMA, BMI1/2, POPCNT/LZCNT, AES/SHA-NI, GFNI, VAES, VPCLMULQDQ.
Measurement noise
Samples- Minimum delta- Median baseline- Mean delta- Maximum delta- Sigma-
Wikimedia Commons block diagram of Intel Gracemont E-core architecture
Gracemont E-core diagram shown for the E-core worker. GracemontRevised.png by Saneandsad, licensed CC BY-SA 4.0 via Wikimedia Commons.
Timing delta from median
period
AMD Zen 4 active zen4
uarch Zen 4
core class Zen 4 core
Cores
1 isolated Ryzen 5 7500F core (of 6), SMT sibling offline, fixed at 3.7 GHz.
Cache
32 KiB L1D 8-way, 32 KiB L1I 8-way, 1 MiB private L2 8-way, 32 MiB shared L3 16-way, 64 B lines.
DRAM
16 GiB DDR5 on an AM5/A620 platform, single NUMA node.
Front end
4-wide decode, op cache delivering up to 9 ops/cycle, 6-wide rename and dispatch.
OoO engine
6-wide dispatch, 8-wide retire, 320-entry reorder buffer, 6 integer pipes and 4 x 256-bit FP/vector pipes.
ISA highlights
AVX2, AVX-512F/DQ/BW/VL/VNNI/BF16/VBMI/VBMI2/IFMA, FMA, BMI1/2, AES/SHA-NI, GFNI, VAES, VPCLMULQDQ.
Measurement noise
Samples- Minimum delta- Median baseline- Mean delta- Maximum delta- Sigma-
Block diagram of AMD Zen 4 core architecture
Zen 4 frontend, execution engine, and cache hierarchy for the Ryzen 5 7500F worker. Diagram from AMD's Zen 4 Part 1: Frontend and Execution Engine by Chips and Cheese.
Timing delta from median
period
RTX 4000 Ada + AMD Zen 4 active rtx_4000_ada
uarch Ada
core class custom
Cores
Configured by the judge worker for this system.
Cache
No static cache description is registered for this system yet.
DRAM
No static DRAM topology is registered for this system yet.
Front end
No static front-end summary is registered for this system yet.
OoO engine
No static out-of-order engine summary is registered for this system yet.
ISA highlights
No static CPU feature list is registered for this system yet.
Measurement noise
Samples- Minimum delta- Median baseline- Mean delta- Maximum delta- Sigma-
Timing delta from median
period
02 raptor lake die
Labelled Intel Core i9-13900K Raptor Lake die shot
Raptor Lake family i9-13900K die shot shown for orientation; the current host is an i5-13500. Image by JmsDoug and Fritzchens Fritz, licensed CC0 via Wikimedia Commons.